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rev. 1.0 7/13 copyright ? 2013 by silicon laboratories si5328 si5328 itu-t g.8262 s ynchronous e thernet j itter -a ttenuating c lock m ultiplier features applications description the si5328 is a jitter-attenuating precision clock multiplier for synchronous ethernet app lications requiring sub 1 ps jitter performance and ultra-low loop bandwidth. when combined with a low-wander, low- jitter reference oscillato r, the si5328 meets a ll of the wander, mtie, tdev, and other requirements listed in itu-t g.8262/y.1362. the si5328 accepts two input clocks ranging from 8 khz to 710 mhz and generates two output clocks ranging from 8 khz to 808 mhz. the two outputs are divided down separately from a common source. the si5328 can also use the tcxo as a clock source for frequency synthesis. the device provides virtually any frequency tr anslation combination across this operating range. the si5328 input clock frequency and clock multiplication ratio are programmable through an i 2 c or spi interface. the si5328 is based on silicon laboratories' third-generation dspll ? technology, which provides frequency synthesis and jitter attenuation in a highly integrated pll solution that e liminates the need for external vcxo and loop filter components. the dspll loop bandwidth is digitally programmable, providing jitter perform ance optimization at the application level. operating from a single 2.5 or 3.3 v supply, the si5328 is ideal for providing clock multiplication and jit ter attenuation in high-performance, synchronous ethernet timing applications. ? fully-compliant with itu-t g.8262, eec options 1 and 2. ? generates any frequency from 8khz to 808mhz. ? ultra-low jitter clock outputs with jitter generation as low as 0.3 ps rms (12 khz?20 mhz) ? integrated loop filter with selectable loop bandwidth (0.1 hz; 1 to 10 hz) ? dual clock inputs with manual or automatically controlled hitless switching ? dual clock outputs with selectable signal format (lvpecl, lvds, cml, cmos) ? lol, los, fos alarm outputs ? i 2 c or spi programmable ? on-chip voltage regulator for 2.5 10% or 3.3 v 10% operation ? small size: 6 x 6 mm 36-lead qfn ? pb-free, rohs compliant ? g.8262 synchronous ethernet, eec options 1 and 2 ? gbe/10gbe/100gbe synchronous ethernet ? carrier ethern et switches, routers ordering information: see page 63. pin assignments 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 nc nc rst c2b int_c1b gnd vdd xa vdd rate0 ckin2+ ckin2? nc rate1 ckin1+ ckin1? cs_ca scl sda_sdo a1 a2_ss sdi ckout1? nc gnd vdd nc ckout2? ckout2+ cmode gnd pad a0 nc 9 18 19 28 xb lol nc ckout1+
si5328 2 rev. 1.0 functional block diagram dspll ? loss of signal/ frequency offset tcxo or refclock ckout2 ckin1 ckout1 ckin2 n31 n2 n1_ls n2_ls signal detect device interrupt vdd (2.5 or 3.3 v) gnd n32 loss of lock clock select i 2 c/spi port control rate select n1_hs refclock hitless switching mux
si5328 rev. 1.0 3 t able of c ontents 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical phase noise perf ormance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.1. external xaxb reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2. further documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6. register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 7. pin descriptions: si5328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9. package outline: 36-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10. recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11. si5328 device top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
si5328 4 rev. 1.0 1. electrical specifications figure 1. differential voltage characteristics figure 2. rise/fall time characteristics table 1. recommended operating conditions parameter symbol test condition min typ max unit ambient temperature t a ?40 25 85 c supply voltage during normal operation v dd 3.3 v nominal 2.97 3.3 3.63 v 2.5 v nominal 2.25 2.5 2.75 v note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 oc unless otherwise stated. v ise , v ose v id ,v od differential i/os v icm , v ocm single-ended peak-to-peak voltage differential peak-to-peak voltage signal + signal ? (signal +) ? (signal ?) v t signal + signal ? v id = (signal+) ? (signal?) v icm , v ocm t f t r 80% 20% ckin, ckout
si5328 rev. 1.0 5 table 2. dc characteristics (v dd = 2.5 v 10% or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit supply current 1 i dd lvpecl format 808 mhz out both ckouts enabled ? 251 279 ma lvpecl format 808 mhz out 1 ckout enabled ? 217 243 ma cmos format 25 mhz out both ckouts enabled ? 204 234 ma cmos format 25 mhz out 1 ckout enabled ? 194 220 ma disable mode ? 165 ? ma ckinn input pins 2 input common mode voltage (input thresh- old voltage) v icm 2.5 v 10% 1 ? 1.7 v 3.3 v 10% 1.1 ? 1.95 v input resistance ckn rin single-ended 20 40 60 k ? single-ended input voltage swing (see absolute specs) v ise f ckin <212.5mhz see figure 1. 0.2 ? ? v pp f ckin >212.5mhz see figure 1. 0.25 ? ? v pp differential input voltage swing (see absolute specs) v id f ckin <212.5mhz see figure 1. 0.2 ? ? v pp fckin > 212.5 mhz see figure 1. 0.25 ? ? v pp notes: 1. current draw is independent of supply voltage 2. no under- or overshoot is allowed. 3. lvpecl, cml, lvds and low-swing lvds measured wi th fo = 312.5 mhz. 4. this is the amount of leakage that the 3-level inputs can tolerate from an external driver. see si53xx family reference manual for more details.
si5328 6 rev. 1.0 output clocks (ckoutn) common mode cko vcm lvpecl 100 ? load line- to-line v dd ?1.42 ? v dd ?1.25 v differential output swing 3 cko vd lvpecl 100 ? load line- to-line 1.1 ? 1.9 v pp single ended output swing 3 cko vse lvpecl 100 ? load line- to-line 0.5 ? 0.93 v pp differential output voltage 3 cko vd cml 100 ? load line-to- line 350 425 500 mv pp common mode output voltage 3 cko vcm cml 100 ? load line-to- line ?v dd ?0.36 ? v differential output voltage 3 cko vd lvds 100 ? load line-to-line 500 700 900 mv pp low swing lvds 100 ? load line-to-line 350 425 500 mv pp common mode output voltage 3 cko vcm lvds 100 ??load line-to- line 1.125 1.2 1.275 v differential output resistance cko rd cml, lvpecl, lvds ? 200 ? ? output voltage low cko vollh cmos ? ? 0.4 v output voltage high cko vohlh v dd =2.25v cmos 0.8 x v dd ??v table 2. dc characteristics (continued) (v dd = 2.5 v 10% or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. current draw is independent of supply voltage 2. no under- or overshoot is allowed. 3. lvpecl, cml, lvds and low-swing lvds measured wi th fo = 312.5 mhz. 4. this is the amount of leakage that the 3-level inputs can tolerate from an external driver. see si53xx family reference manual for more details.
si5328 rev. 1.0 7 output drive current (cmos driving into cko vol for output low or cko voh for output high. ckout+ and ckout? shorted externally) cko io icmos[1:0] =11 v dd =2.5v ?20 ?ma icmos[1:0] =10 v dd =2.5v ?15 ?ma icmos[1:0] =01 v dd =2.5v ?10 ?ma icmos[1:0] =00 v dd =2.5v ?5 ?ma icmos[1:0] = 11 v dd =3.3v ?32 ?ma icmos[1:0] =10 v dd =3.3v ?24 ?ma icmos[1:0] =01 v dd =3.3v ?16 ?ma icmos[1:0] =00 v dd =3.3v ?8 ?ma 2-level lvcmos input pins input voltage low v il v dd =2.25v ? ? 0.7 v v dd =2.97v ? ? 0.8 v input voltage high v ih v dd =2.25v 1.8 ? ? v v dd =3.63v 2.5 ? ? v table 2. dc characteristics (continued) (v dd = 2.5 v 10% or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. current draw is independent of supply voltage 2. no under- or overshoot is allowed. 3. lvpecl, cml, lvds and low-swing lvds measured wi th fo = 312.5 mhz. 4. this is the amount of leakage that the 3-level inputs can tolerate from an external driver. see si53xx family reference manual for more details.
si5328 8 rev. 1.0 3-level input pins 4 input voltage low v ill ? ? 0.15 x v dd v input voltage mid v imm 0.45 x v dd ?0.55xv dd v input voltage high v ihh 0.85 x v dd ??v input low current i ill see note 4 ?20 ? ? a input mid current i imm see note 4 ?2 ? +2 a input high current i ihh see note 4 ? ? 20 a lvcmos output pins output voltage low v ol io = 2 ma v dd =2.25v ?? 0.4v output voltage low io = 2 ma v dd =2.97v ?? 0.4v output voltage high v oh io = ?2 ma v dd =2.25v v dd ?0.4 ? ? v output voltage high io = ?2 ma v dd =2.97v v dd ?0.4 ? ? v disabled leakage current i oz rstb = 0 ?100 ? 100 a table 2. dc characteristics (continued) (v dd = 2.5 v 10% or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. current draw is independent of supply voltage 2. no under- or overshoot is allowed. 3. lvpecl, cml, lvds and low-swing lvds measured wi th fo = 312.5 mhz. 4. this is the amount of leakage that the 3-level inputs can tolerate from an external driver. see si53xx family reference manual for more details.
si5328 rev. 1.0 9 table 3. ac characteristics (v dd = 2.5 10% or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit single-ended reference clock input pin xa (xb with cap to gnd) input resistance xa rin rate[1:0] = lm, ml, mh, ac coupled ?12? k ? input voltage swing xa vpp rate[1:0] = lm, ml, mh, ac coupled 0.5 ? 1.2 v pp differential reference cl ock input pins (xa/xb) input voltage swing xa/xb vpp rate[1:0] = lm, ml, mh 0.5 ? 1.2 v pp , each. ckinn input pins input frequency ckn f 0.008 ? 710 mhz input duty cycle (minimum pulse width) ckn dc input frequency > 225 mhz 40 ? 60 % input frequency < 225 mhz refers to both high and low widths 2??ns input capacitance ckn cin ?? 3 pf input rise/fall time ckn trf 20?80% see figure 2 ??11 ns ckoutn output pins (see ordering section for speed grade vs frequency limits) output frequency (output not config- ured for cmos) cko f n1 ? 6 0.008 ? 808 mhz maximum output frequency in cmos format cko f ? ? 212.5 mhz output rise/fall (20?80%) @ 212.5 mhz output cko trf cmos output v dd =2.25 c load =5pf ?? 8 ns output rise/fall (20?80%) @ 212.5 mhz output cko trf cmos output v dd =2.97 c load =5pf ?? 2 ns notes: 1. lock and settle times may change with different f3, loop bw, and vco frequency values. contact silicon labs for further details. 2. see section 9 of ?an775: si5328 synchronous ether net compliance test report? for more details.
si5328 10 rev. 1.0 output rise/fall (20?80%) @ 312.5 mhz output cko trf lvpecl, lvds or cml output ?230350 ps output duty cycle uncertainty @ 808 mhz cko dc 100 ? load line-to-line measured at 50% point (not for cmos) 45 ? 55 % lvcmos input pins minimum reset pulse width t rstmn 1 s reset to microproces- sor access ready t ready 10 ms input capacitance c in ?? 3 pf lvcmos output pins rise/fall times t rf c load =20pf see figure 2 ?25? ns losn trigger window los trig from last ckinn ?? to ? internal detection of losn n3 1 ??4.5 x n3t ckin time to clear lol after los cleared t clrlol ? los to ? lol fold = fnew stable xa/xb reference ?10? ms device skew output clock skew t skew ? of ckoutn to ? of ckout_m, ckoutn and ckout_m at same frequency and signal format phaseoffset =0 ckout_always_on =1 sq_ical =1 ??100ps phase change due to temperature variation t temp max phase changes from ? 40 to +85 c, stable xaxb reference ?300500 ps table 3. ac characteristics (continued) (v dd = 2.5 10% or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. lock and settle times may change with different f3, loop bw, and vco frequency values. contact silicon labs for further details. 2. see section 9 of ?an775: si5328 synchronous ether net compliance test report? for more details.
si5328 rev. 1.0 11 pll performance (fin = fout = 346 mhz; bw = 0.088 hz; lvpecl) lock time 1 t lockmp start of ical to lol low, lockt = 4, fastlock enabled ?2? s start of ical to lol low, lockt = 1, fastlock enabled ?12.5? s settle time 1 t settle start of ical to output phase within 45 degrees of final value, lockt = 4, fastlock enabled ?1? s start of ical to output phase within 45 degrees of final value, lockt = 1, fastlock enabled ?1? s output clock phase change t p_step after clock switch f3 ? 128 khz ?200? ps closed loop jitter peaking j pk ?0.050.2 db jitter/wander to l e r a n c e 2 j tol jitter frequency ?? loop bandwidth 5000/bw ? ? ns pk-pk phase noise fout = 156.25 mhz cko pn 1 khz offset ? ?120 ? dbc/hz 10 khz offset ? ?128 ? dbc/hz 100 khz offset ? ?130 ? dbc/hz 1 mhz offset ? ?144 ? dbc/hz subharmonic noise sp subh phase noise @ 100 khz offset ??88? dbc spurious noise sp spur max spur @ n x f3 (n ? 1, n x f3 < 100 mhz) ??93? dbc table 3. ac characteristics (continued) (v dd = 2.5 10% or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. lock and settle times may change with different f3, loop bw, and vco frequency values. contact silicon labs for further details. 2. see section 9 of ?an775: si5328 synchronous ether net compliance test report? for more details.
si5328 12 rev. 1.0 table 4. microprocessor control (v dd = 2.5 10% or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit i 2 c bus lines (sda, scl) input voltage low vil i2c ? ? 0.25 x v dd v input voltage high vih i2c 0.7 x v dd ?v dd v input current ii i2c vin = 0.1 x v dd to 0.9 x v dd ?10 ? 10 a hysteresis of schmitt trigger inputs vhys i2c 0.05 x v dd ?? v output voltage low vol i2c io = 3 ma ? ? 0.4 v
si5328 rev. 1.0 13 spi specifications duty cycle, sclk t dc sclk = 10 mhz 40 ? 60 % cycle time, sclk t c 100 ? ? ns rise time, sclk t r 20?80% ? ? 25 ns fall time, sclk t f 20?80% ? ? 25 ns low time, sclk t lsc 20?20% 30 ? ? ns high time, sclk t hsc 80?80% 30 ? ? ns delay time, sclk fall to sdo active t d1 ?? 25 ns delay time, sclk fall to sdo transition t d2 ?? 25 ns delay time, ss rise to sdo tri-state t d3 ?? 25 ns setup time, ss to sclk fall t su1 25 ? ? ns hold time, ss to sclk rise t h1 20 ? ? ns setup time, sdi to sclk rise t su2 25 ? ? ns hold time, sdi to sclk rise t h2 20 ? ? ns delay time between slave selects t cs 25 ? ? ns table 4. microprocessor control (continued) (v dd = 2.5 10% or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit
si5328 14 rev. 1.0 table 5. jitter generation 1,2,3,4,5,6 symbol filter output frequency min typ max unit jgen 12 khz to 20 mhz 125 mhz ? 331 ? fs, rms jgen 10 khz to 1 mhz 125 mhz ? 287 ? fs, rms jgen 12 khz to 20 mhz 156.25 mhz ? 308 ? fs, rms jgen 10 khz to 1 mhz 156.25 mhz ? 263 ? fs, rms notes: 1. input frequency = 25 mhz. 2. xaxb reference = rakon 40 mhz tcxo mode l rtx7050a, part number 509768. 3. vdd=3.3v. 4. clock output = lvpecl. 5. loop bandwidth = 0.085 hz. 6. using agilent e5052b.
si5328 rev. 1.0 15 table 6. thermal characteristics (v dd = 2.5 10% or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition value unit thermal resistance junction to ambient ? ja still air 32 c/w thermal resistance junction to case ? jc still air 14 c/w table 7. absolute maximum ratings parameter symbol test condition min typ max unit dc supply voltage v dd ?0.5 ? 3.8 v lvcmos input voltage v dig ?0.3 v dd +0.3 v ckinn voltage level limits ckn vin 0?v dd v xa/xb voltage level limits xa vin 0?1.2v operating junction temperature t jct ?55 ? 150 oc storage temperature range t stg ?55 ? 150 oc esd hbm tolerance (100 pf, 1.5 k ? ); all pins except ckin+/ckin? 2??kv esd mm tolerance; all pins except ckin+/ckin? 150 ? ? v esd hbm tolerance (100 pf, 1.5 k ? ); ckin+/ckin? 750 ? ? v esd mm tolerance; ckin+/ckin? 100 ? ? v latch-up tolerance jesd78 compliant *note: permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions specified in the operation sections of this data s heet. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
si5328 16 rev. 1.0 2. typical phase noise performance figure 3. typical phase noise plot table 8. rms jitter values jitter band jitter (rms) 10 khz to 1 mhz 263 fs 12 khz to 20 mhz 309 fs notes: 1. input frequency = 25 mhz. 2. xaxb reference = rakon 40 mhz tcxo model rtx7050a, part number 509768. 3. vdd=3.3v. 4. clock output = lvpecl. 5. loop bandwidth = 0.085 hz. 6. using agilent e5052b.
si5328 rev. 1.0 17 3. typical application circuit note: for an example schematic and layout, refer to the si5328-evb user?s guide. figure 4. si5328 typical application circuit (i 2 c control mode) gnd pad si5328 rst ckout1+ ckout1? vdd gnd ferrite bead system power supply c 1 c 2 c 3 reset clock outputs ckout2+ ckout2? cmode control mode (l) 100 ? 0.1 f 0.1 f + ? 100 ? 0.1 f 0.1 f + ? c 4 0.1 f 0.1 f 0.1 f 1 f notes: 1. assumes differential lvpecl termination (3.3 v) on clock inputs. 2. denotes tri-level input pins with states designated as l (ground), m (vdd/2), and h (vdd). 3. i 2 c-required pull-up resistors not shown. xa xb refclk+ 0.1 f refclk? 0.1 f rate[1:0] 2 ref clk rate v dd 15 k ? input clock sources* ckin2+ ckin2? 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v ckin1+ ckin1? gnd pad 15 k ? int_c1b interrupt/ckin1 invalid indicator c2b ckin2 invalid indicator lol pll loss of lock indicator serial data serial clock sda scl i 2 c interface serial port address a[2:0] clock select/clock active cs_ca
si5328 18 rev. 1.0 figure 5. si5328 typical application circuit (spi control mode) si5328 rst ckout1+ ckout1? vdd gnd ferrite bead system power supply c 1 c 2 c 3 reset clock outputs ckout2+ ckout2? cmode control mode (h) ckin2+ ckin2? 100 ? 0.1 f 0.1 f + ? 100 ? 0.1 f 0.1 f + ? c 4 0.1 f 0.1 f 0.1 f 1 f ckin1+ ckin1? spi interface serial data out serial data in sdo sdi serial clock sclk slave select ss clock select/clock active cs_ca gnd pad notes: 1. assumes differential lvpecl termination (3.3 v) on clock inputs. 2. denotes tri-level input pins with states designated as l (ground), m (vdd/2), and h (vdd). input clock sources* 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v xa xb refclk+ 0.1 f refclk? 0.1 f rate[1:0] 2 ref clk rate v dd 15 k ? 15 k ? int_c1b interrupt/clkin1 invalid indicator c2b clkin2 invalid indicator lol pll loss of lock indicator
si5328 rev. 1.0 19 4. functional description figure 6. functional block diagram the si5328 is a jitter-attenuating precision clock multiplier for synchronous ethernet applications requiring sub 1 ps jitter performance and ultra-low loop bandwidth. when comb ined with a low-wander reference oscillator, the si5 328 meets all of the wander, mtie, tdev, and other requirements that are listed in itu-t g.8262/y.1362. the si5328 accepts two input clocks ranging from 8 khz to 710 mhz and generates two output clocks ranging from 8 khz to 808 mhz. the si5328 can also use its tcxo as a clock source for frequency synthesis. the device provides virtually any frequency translation combination across this operating range. independent dividers are available for each input clock and output clock, so the si5328 can accept input clocks at different frequ encies and it can generate output clocks at different frequencies. the si5328 input clock frequency and clock multiplication ratio are programmable through an i 2 c or spi interface. silicon laboratories offers a pc-based software utility, dspll sim , that can be used to determine the optimum pll divider settings for a given input frequency/clock multiplication ratio combinat ion that minimizes phase noise and power consumpt ion. this utility can be downloaded from http://www.silabs.com/timing . the si5328 is based on s ilicon laboratories' 3rd- generation dspll ? technology, which provides any frequency synthesis and jitter attenuation in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the si5328 pll loop bandwidth is digitally programmable and supports a range from less than 0.1 hz to 6 hz. the dspll sim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. the si5328 supports hitless switching between the two synchronous input clocks in compliance with g.8262 that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (maximum 200 ps phase transient). manual and automatic revertive and non-revertive input clock switching options are available. the si5328 monitors both input clocks for loss-of-signal (los) and provides a los alarm (int_c1b and c2b) when it detects missing pulses on either input cloc k. the device monitors the lock status of the pll. the lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. the si5328 also monitors frequency offset alarms (fos), which indicate if an input cl ock is within a specified frequency band relative to the frequency of a reference clock. both stratum 3/3e and sonet minimum clock (smc) fos thresholds are supported.the si5328 provides a digital hold capab ility that allows the device to continue generation of a stable output clock when the selected input reference is lost. during digital hold, the dspll generates an output frequency based on a historical average frequency that existed for a fixed amount of time before the error event occurred, eliminating the effects of phase and frequency transients that may occur immediately preceding digital hold. the si5328 has two differential clock outputs. the electrical format of each clock output is independently programmable to support lvpecl, lvds, cml, or cmos loads. if not required, the second clock output can be powered down to minimize power consumption. dspll ? loss of signal/ frequency offset tcxo or refclock ckout2 ckin1 ckout1 ckin2 n31 n2 n1_ls n2_ls signal detect device interrupt vdd (2.5 or 3.3 v) gnd n32 loss of lock clock select i 2 c/spi port control rate select n1_hs refclock hitless switching mux
si5328 20 rev. 1.0 the phase of one output clock may be adjusted in relation to the phase of the other output clock with resolution that varies from 800 ps to 2.2 ns, depending on the pll divider settings. see table 9 for instructions on ensuring output-to-output alignment. the input to output skew is not specif ied or controlled. the dspll sim software utility determ ines the phase offset resolution for a given inpu t clock/clock multiplication ratio combination. for system-level debugging, a bypass mode is available which drives the output clock directly from the input cl ock, bypassing the internal dspll. the device is powere d by a single 2.5 or 3.3 v supply. 4.1. external xaxb reference in order to achieve the levels of performance required by g.8262, care must be exercised when selecting an xa/xb reference. to meet the wander spec ifications in g.8262, a tcxo or ocxo will be needed. ?an775: si5328 itu-t g.8262 synce compliance test report? is a g.8262 test report using a 40 mhz rakon rtx7050a-109 tcxo. see ?an776: using the si5328 in a g.8262 compliant synce application? for a discussion of how to select and best use a tcxo as well as a list of other potential tcxo sources. 4.2. further documentation consult the silicon laboratories si53xx any frequency precision clock family re ference manual (frm) for detailed information about the si5328 functions. additional design support is available from silicon laboratories through your distributor. silicon laboratories has developed a pc-based software utility called dspll sim to simplify device configuration, including frequency planning and loop bandwidth selection. the frm and this utility can be downloaded from http://www.silabs.com/timing . table 9. ckout_always_on and sq_ical truth table ckout_always_on sq_ical results 0 0 ckout off until after the first ical 0 1 ckout off until after the first successful ical (i.e., when lol is low) 1 0 ckout always on, including during an ical 1 1 ckout always on, including during an ical. use these settings to pr eserve output-to-output skew
si5328 rev. 1.0 21 5. register map all register bits that are not defined in this map should alwa ys be written with the specified re set values. the writing to the se bits of values other than the specified reset values may result in undefined device behavior. registers not listed, such as register 64, should never be writ ten to. register d7 d6 d5 d4 d3 d2 d1 d0 0 free_run ckout_always_on bypass_reg 1 ck_prior2[1:0] ck_prior[1:0] 2 bwsel_reg[3:0] 3 cksel_reg[1:0] dhold sq_ical 4 autosel_reg[1:0] hst_del[4:0] 5 icmos[1:0] 6 sleep sfout2_reg[2:0] sfout1_reg[2:0] 7 fosrefsel[2:0] 8 hlog_2[1:0] hlog_1[1:0] 9 hist_avg[4:0] 10 dsbl2_ reg dsbl1_ reg 11 pd_ck2 pd_ck1 19 fos_en fos_thr[1:0] va ltime[1:0] lock[t2:0] 20 ck2_bad_pin ck1_ bad_ pin lol_pin int_pin 21 ck1_actv_pin cksel_pin 22 ck_actv_ pol ck_bad_ pol lol_pol int_pol 23 los2_msk los1_msk losx_msk 24 fos2_msk fos1_msk lol_msk 25 n1_hs[2:0] 31 nc1_ls[19:16] 32 nc1_ls[15:8] 33 nc1_ls[7:0] 34 nc2_ls[19:16]
22 rev. 1.0 si5328 35 nc2_ls[15:8] 36 nc2_ls[7:0] 40 n2_hs[2:0] n2_ls[19:16] 41 n2_ls[15:8] 42 n2_ls[7:0] 43 n31[18:16] 44 n31[15:8] 45 n31[7:0] 46 n32[18:16] 47 n32[15:8] 48 n32[7:0] 55 clkin2rate[2:0] clkin1rate[2:0] 128 ck2_actv_reg ck1_actv_reg 129 los2_int los1_int losx_int 130 digholdvalid fos2_int fos1_int lol_int 131 los2_flg los1_flg losx_flg 132 fos2_flg fos1_flg lol_flg 134 partnum_ro[11:4] 135 partnum_ro[3:0] revid_ro[3:0] 136 rst_reg ical grade_ro[1:0] 137 fastlock 138 los2_en [1:1] los1_en [1:1] 139 los2_en[0:0] los1_en[0:0] fos2_en fos1_en 142 independentskew1[7:0] 143 independentskew2[7:0] register d7 d6 d5 d4 d3 d2 d1 d0
si5328 rev. 1.0 23 6. register descriptions reset value = 0001 0100 register 0. bitd7 d6 d5 d4d3d2 d1 d0 name free_run ckout_always_on bypass_reg type r r/w r/w rrr r/w r bit name function 7 reserved reserved. 6 free_run free run. internal to the device, route xa/xb to ckin2. this allows the device to lock to its xa-xb reference. 0: disable 1: enable 5 ckout_always_on ckout always on. this will bypass the sq_ical function. ou tput will be availabl e even if sq_i- cal is on and ical is not complete or successful. see table 9 on page 20. 0: squelch output until pa rt is calibrated (ical). 1: provide an output. note: the frequency may be significantly off and variable until the part is calibrated. 4:2 reserved reserved. 1 bypass_reg bypass register. this bit enables or disables the pll by pass mode. use only when the device is in digital hold or before the first ical. 0: normal operation 1: bypass mode. selected input clock is connected to ckout buffers, bypass- ing the pll. bypass mode does not support cmos clock outputs. 0 reserved reserved.
si5328 24 rev. 1.0 reset value = 1110 0100 reset value = 0100 0010 register 1. bitd7d6d5d4 d3 d2 d1 d0 name reserved ck_prior2 [1:0] ck_prior1 [1:0] type rr / w r / w bit name function 7:4 reserved reserved. 3:2 ck_prior2 [1:0] ck_prior 2. selects which of the input clocks will be 2nd priority in the autoselection state machine. 00: ckin1 is 2nd priority. 01: ckin2 is 2nd priority. 10: reserved 11: reserved 1:0 ck_prior1 [1:0] ck_prior 1. selects which of the input clocks will be 1st priority in the autoselection state machine. 00: ckin1 is 1st priority. 01: ckin2 is 1st priority. 10: reserved 11: reserved register 2. bitd7d6d5d4d3d2d1d0 name bwsel_reg [3:0] reserved type r/w r bit name function 7:4 bwsel_reg [3:0] bwsel_reg. selects nominal f3db bandwidth for pll. see dspll sim for settings. after bwsel_reg is written with a new value, an ical is required for the change to take effect. 3:0 reserved reserved.
si5328 rev. 1.0 25 reset value = 0000 0101 register 3. bitd7d6d5d4d3d2d1d0 name cksel_reg [1:0] dhold sq_ical reserved type r/w r/w r/w r bit name function 7:6 cksel_reg [1:0] cksel_reg. if the device is operating in regi ster-based manual clock selection mode (autosel_reg = 00), and cksel_pin = 0, th en these bits select which input clock will be the active input clock. if cksel_pin = 1 and autosel_reg = 00, the cs_ca input pin continues to control clock selection and cksel_reg is of no consequence . 00: ckin_1 selected. 01: ckin_2 selected. 10: reserved 11: reserved 5 dhold dhold. forces the part into digital hold. this bit overrides all other manual and automatic clock selection controls. 0: normal operation. 1: force digital hold mode. overrides all other settings and ignores the quality of all of the input clocks. 4 sq_ical sq_ical. this bit determines if the output clocks will remain enab led or be squelched (dis- abled) during an internal calibration. see table 9 on page 20. 0: output clocks enabled during ical. 1: output clocks disabled during ical. 3:0 reserved reserved.
si5328 26 rev. 1.0 reset value = 0001 0010 reset value = 1110 1101 register 4. bitd7d6d5d4d3d2d1d0 name autosel_reg [1:0] reserved hist_del [4:0] type r/w r r/w bit name function 7:6 autosel_reg [1:0] autosel_reg [1:0] . selects method of input cl ock selection to be used. 00: manual (eithe r register or pin cont rolled, see cksel_pin) 01: automatic non-revertive 10: automatic revertive 11: reserved see the si53xx family reference manual for a detailed description. 5 reserved reserved. 4:0 hist_del [4:0] hist_del [4:0]. selects amount of delay to be used in generating the history information used for digital hold. see the si53xx family reference manual for a detailed description. register 5. bitd7d6d5d4d3d2d1d0 name icmos [1:0] reserved type r/w r bit name function 7:6 icmos [1:0] icmos [1:0]. when the output buffer is set to cmos mode, these bits determine the output buffer drive strength. the first number below refers to 3.3 v operation; the second to 2.5 v operation. these values assume ckout+ is tied to ckout?. 00: 8ma/5ma 01: 16 ma/10 ma 10: 24 ma/15 ma 11: 32 ma/20 ma 5:0 reserved reserved.
si5328 rev. 1.0 27 reset value = 0010 1101 register 6. bitd7 d6d5d4d3d2d1d0 name reserved sleep sfout2_reg [2:0] sfout1_reg [2:0] type rr/w r/w r/w bit name function 7 reserved reserved. 6 sleep sleep. in sleep mode, all clock outputs are disabled and the maximum amount of internal circuitry is powered down to reduce powe r dissipation and noise generation. this bit overrides the sfoutn_reg[2:0] output signal format settings. 0: normal operation 1: sleep mode 5:3 sfout2_reg [2:0] sfout2_reg [2:0]. controls output signal format and disable for ckout2 output buffer. 000: reserved 001: disable 010: cmos (bypass mode not supported) 011: low swing lvds 100: reserved 101: lvpecl 110: cml 111: lvds 2:0 sfout1_reg [2:0] sfout1_reg [2:0]. controls output signal format and disable for ckout1 output buffer. 000: reserved 001: disable 010: cmos (bypass mode not supported) 011: low swing lvds 100: reserved 101: lvpecl 111: lvds
si5328 28 rev. 1.0 reset value = 0010 1010 register 7. bitd7d6d5d4d3d2d1d0 name reserved fosrefsel [2:0] type rr/w bit name function 7:3 reserved. reserved. 2:0 fosrefsel [2:0] fosrefsel [2:0]. selects which input clock is used as the reference frequency for frequency offset (fos) alarms. 000: xa/xb (external reference) 001: ckin1 010: ckin2 011: reserved 100: reserved 101: reserved 110: reserved 111: reserved
si5328 rev. 1.0 29 reset value = 0000 0000 reset value = 1100 0000 register 8. bitd7d6d5d4d3d2d1d0 name hlog_2[1:0] hlog _1[1:0] reserved type r/w r/w r bit name function 7:6 hlog_2 [1:0] hlog_2 [1:0]. 00: normal operation 01: holds ckout2 output at st atic logic 0. entrance and ex it from this state will occur without glitches or runt pulses. 10: holds ckout2 output at st atic logic 1. entrance and ex it from this state will occur without glitches or runt pulses. 11: reserved 5:4 hlog_1 [1:0]. 00: normal operation 01: holds ckout1 output at st atic logic 0. entrance and ex it from this state will occur without glitches or runt pulses. 10: holds ckout1 output at st atic logic 1. entrance and ex it from this state will occur without glitches or runt pulses. 11: reserved 3:0 reserved reserved. register 9. bitd7d6d5d4d3d2d1d0 name hist_avg [4:0] reserved type r/w rrr bit name function 7:3 hist_avg [4:0] hist_avg [4:0]. selects amount of averaging time to be used in generating the history information for digital hold. see the si53xx family reference manual for a detailed description 2:0 reserved reserved.
si5328 30 rev. 1.0 reset value = 0000 0000 register 10. bit d7d6d5d4 d3 d2 d1 d0 name reserved dsbl2_reg dsbl1_reg reserved reserved type rr/wr/wrr bit name function 7:4 reserved reserved. 3 dsbl2_reg dsbl2_reg. this bit controls the powerdown of the ck out2 output buffer. if disable mode is selected, the n2_ls output divider is also powered down. 0: ckout2 enabled 1: ckout2 disabled 2 dsbl1_reg dsbl1_reg. this bit controls the powerdown of the ck out1 output buffer. if disable mode is selected, the n1_ls output divider is also powered down. 0: ckout1 enabled 1: ckout1 disabled 1:0 reserved reserved.
si5328 rev. 1.0 31 reset value = 0100 0000 register 11. bitd7d6d5d4d3d2d1d0 name reserved pd_ck2 pd_ck1 type rr/wr/w bit name function 7:2 reserved reserved. 1pd_ck2 pd_ck2. this bit controls the powerdown of the ckin2 input buffer. 0: ckin2 enabled 1: ckin2 disabled 0pd_ck1 pd_ck1. this bit controls the powerdown of the ckin1 input buffer. 0: ckin1 enabled 1: ckin1 disabled
si5328 32 rev. 1.0 reset value = 0010 1100 register 19. bitd7d6d5d4d3d2d1d0 name fos_en fos_thr [1:0] valtime [1:0] lockt [2:0] type r/w r/w r/w r/w bit name function 7fos_en fos_en. frequency offset enable globally disables fos. see the individual fos enables (fosx_en, register 139). 0: fos disable 1: fos enabled by fosx_en 6:5 fos_thr [1:0] fos_thr [1:0]. frequency offset at which fos is declared (relative to the selected fos reference): 00: 11 to 12 ppm (stratum 3/3e compliant, with a stratum 3/3e used for refclk 01: 48 to 49 ppm (smc) 10: 30 ppm (sonet minimum clock (smc), with a stratum 3/3e used for refclk. 11: 200 ppm 4:3 valtime [1:0] valtime [1:0]. sets amount of time for input clock to be valid before the associated alarm is removed. 00: 2 ms 01: 100 ms 10: 200 ms 11: 13 seconds 2:0 lockt [2:0] lockt [2:0]. sets retrigger interval for one shot monitori ng phase detector output. one shot is trig- gered by phase slip in dspll. refer to the si53xx family reference manual for more details. 000: 106 ms 001: 53 ms 010: 26.5 ms 011: 13.3 ms 100: 6.6 ms 101: 3.3 ms 110: 1.66 ms 111: .833 ms
si5328 rev. 1.0 33 reset value = 0011 1110 register 20. bit d7d6d5d4 d3 d2 d1 d0 name reserved ck2_bad_pin ck1_bad_pin lol_pin int_pin type rr/wr/wr/wr/w bit name function 7:4 reserved reserved. 3 ck2_bad_pin ck2_bad_pin. the ck2_bad status can be reflected on the c2b output pin. 0: c2b output pin tristated 1: c2b status reflected to output pin 2 ck1_bad_pin ck1_bad_pin. either los1 or int (see int_pin) status can be reflected on the int_c1b output pin. 0: int_c1b output pin tristated 1: los1 or int (see int_pin) status reflected to output pin 1lol_pin lol_pin. the lol_int status bit can be reflected on the lol output pin. 0: lol output pin tristated 1: lol_int status reflected to output pin 0int_pin int_pin. reflects the interrupt status on the int_c1b output pin. 0: interrupt status not displayed on int_c1b output pin. instead, the int_c1b pin indicates when ckin1 is bad. if ck1_bad_pi n = 0, int_c1b output pin is tristated. 1: interrupt status re flected to output pin.
si5328 34 rev. 1.0 reset value = 1111 1111 register 21. bitd7d6d5d4d3d2 d1 d0 name reserved reserved ck1_actv_pin cksel_ pin type r force 1 r r r r r/w r/w bit name function 7:2 reserved reserved. 1 ck1_actv_pin ck1_actv_pin. the ck1_actv_reg status bit can be reflected to the cs_ca output pin using the ck1_actv_pin enable function. ck1_actv_ pin is of consequence only when pin controlled clock selection is not being used. (see cksel_pin) 0: cs_ca output pin tristated. 1: clock active status reflected to output pin. 0 cksel_pin cksel_pin. if manual clock selection is being used, clock selection can be controlled via the cksel_reg[1:0] register bits or the cs_ca input pin. this bit is only active when autosel_reg = manual. 0: cs_ca pin is ignored. cksel_reg[1:0] register bits control clock selection. 1: cs_ca input pin controls clock selection.
si5328 rev. 1.0 35 reset value = 1101 1111 register 22. bitd7d6d5d4 d3 d2 d1 d0 name reserved ck_actv_pol ck_ bad_ pol lol_pol int_pol type r r/w r/w r/w r/w bit name function 7:4 reserved reserved. 3 ck_actv_ pol ck_actv_pol. sets the active polarity for the cs_ca si gnals when reflected on an output pin. 0: active low 1: active high 2 ck_bad_ pol ck_bad_pol. sets the active polarity for the int_c1b and c2b signals when reflected on output pins. 0: active low 1: active high 1 lol_pol lol_pol. sets the active polarity for the lol st atus when reflected on an output pin. 0: active low 1: active high 0int_pol int_pol. sets the active polarity for the interrupt st atus when reflected on the int_c1b output pin. 0: active low 1: active high
si5328 36 rev. 1.0 reset value = 0001 1111 register 23. bitd7d6d5d4d3 d2 d1 d0 name reserved los2_ msk los1_ msk losx_ msk type r r/w r/w r/w bit name function 7:3 reserved reserved. 2los2_msk los2_msk. determines if a los on ckin2 (los2_flg) is used in the generation of an interrupt. writes to this register do not change the value held in the los2_flg register. 0: los2 alarm triggers active interr upt on int_c1b output (if int_pin=1). 1: los2_flg ignored in generating interrupt output. 1los1_msk los1_msk. determines if a los on ckin1 (los1_flg) is used in the generation of an interrupt. writes to this register do not change the value held in the los1_flg register. 0: los1 alarm triggers active interr upt on int_c1b output (if int_pin=1). 1: los1_flg ignored in generating interrupt output. 0losx_msk losx_msk. determines if a los on xa/xb(losx_flg) is used in the generation of an interrupt. writes to this register do not change the value held in the losx_flg register. 0: losx alarm triggers active interrup t on int_c1b output (if int_pin=1). 1: losx_flg ignored in generating interrupt output.
si5328 rev. 1.0 37 reset value = 0011 1111 register 24. bitd7d6d5d4d3 d2 d1 d0 name reserved fos2_msk fos1_msk lol_msk type r r/w r/w r/w bit name function 7:3 reserved reserved. 2 fos2_msk fos2_msk. determines if the fos2_flg is used in the gen eration of an interrupt. writes to this reg- ister do not change the value held in the fos2_flg register. 0: fos2 alarm triggers active interr upt on int_c1b output (if int_pin=1). 1: fos2_flg ignored in generating interrupt output. 1 fos1_msk fos1_msk. determines if the fos1_flg is used in the gen eration of an interrupt. writes to this reg- ister do not change the value held in the fos1_flg register. 0: fos1 alarm triggers active interr upt on int_c1b output (if int_pin=1). 1: fos1_flg ignored in generating interrupt output. 0lol_msk lol_msk. determines if the lol_flg is used in the generation of an interrupt. writes to this regis- ter do not change the value held in the lol_flg register. 0: lol alarm triggers active interrup t on int_c1b output (if int_pin=1). 1: lol_flg ignored in generating interrupt output.
si5328 38 rev. 1.0 reset value = 0010 0000 reset value = 0000 0000 register 25. bitd7d6d5d4d3d2d1d0 name n1_hs [2:0] reserved type r/w r bit name function 7:5 n1_hs [2:0] n1_hs [2:0]. sets value for n1 high speed divider which drives ncn_ls (n = 1 to 2) low-speed divider. 000: n1 = 4 001: n1 = 5 010: n1 = 6 011: n1 = 7 100: n1 = 8 101: n1 = 9 110: n1 = 10 111: n1 = 11 4:0 reserved reserved. register 31. bitd7d6d5d4d3d2d1d0 name reserved nc1_ls [19:16] type rr/w bit name function 7:4 reserved reserved. 3:0 nc1_ls [19:16] nc1_ls [19:16]. sets value for nc1 low-speed divider, which drives ckout1 output. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2 20 valid divider values=[1, 2, 4, 6, ..., 2 20 ]
si5328 rev. 1.0 39 reset value = 0000 0000 reset value = 0011 0001 register 32. bitd7d6d5d4d3d2d1d0 name nc1_ls [15:8] type r/w bit name function 7:0 nc1_ls [15:8] nc1_ls [15:8]. sets value for nc1 low-speed divider, which drives ckout1 output. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2 20 valid divider values=[1, 2, 4, 6, ..., 2 20 ] register 33. bitd7d6d5d4d3d2d1d0 name nc1_ls [7:0] type r/w bit name function 7:0 nc1_ls [19:0] nc1_ls [7:0]. sets value for n1 low-speed divider, wh ich drives ckout1 out put. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2 20 valid divider values=[1, 2, 4, 6, ..., 2 20 ]
si5328 40 rev. 1.0 reset value = 0000 0000 reset value = 0000 0000 register 34. bitd7d6d5d4d3d2d1d0 name reserved nc2_ls [19:16] type rr/w bit name function 7:4 reserved reserved. 3:0 nc2_ls [19:16] nc2_ls [19:16]. sets value for nc2 low-speed divider, which drives ckout2 output. must be 0 or odd. 00000000000000000000=1 00000000000000000001=2 00000000000000000011=4 00000000000000000101=6 ... 11111111111111111111=2 20 valid divider values=[1, 2, 4, 6, ..., 2 20 ] register 35. bitd7d6d5d4d3d2d1d0 name nc2_ls [15:8] type r/w bit name function 7:0 nc2_ls [15:8] nc2_ls [15:8]. sets value for nc2 low-speed divider, which drives ckout2 output. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2 20 valid divider values=[1, 2, 4, 6, ..., 2 20 ]
si5328 rev. 1.0 41 reset value = 0011 0001 register 36. bitd7d6d5d4d3d2d1d0 name nc2_ls [7:0] type r/w bit name function 7:0 nc2_ls [7:0] nc2_ls [7:0]. sets value for nc2 low-speed divider, which drives ckout2 output. must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2 20 valid divider values=[1, 2, 4, 6, ..., 2 20 ]
si5328 42 rev. 1.0 reset value = 1100 0000 register 40. bitd7d6d5d4d3d2d1d0 name n2_hs [2:0] reserved n2_ls [19:16] type r/w r r/w bit name function 7:5 n2_hs [2:0] n2_hs [2:0]. sets value for n2 high speed divider, which drives n2ls low-speed divider. 000: 4 001: 5 010: 6 011: 7 100: 8 101: 9 110: 10 111: 11 4 reserved reserved. 3:0 n2_ls [19:16] n2_ls [19:16]. sets value for n2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 2 20 valid divider values = [2, 4, 6, ..., 2 20 ]
si5328 rev. 1.0 43 reset value = 0000 0000 reset value = 1111 1001 register 41. bitd7d6d5d4d3d2d1d0 name n2_ls [15:8] type r/w bit name function 7:0 n2_ls [15:8] n2_ls [15:8]. sets value for n2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 2 20 valid divider values = [2, 4, 6, ..., 2 20 ] register 42. bitd7d6d5d4d3d2d1d0 name n2_ls [7:0] type r/w bit name function 7:0 n2_ls [7:0] n2_ls [7:0]. sets value for n2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 2 20 valid divider values = [2, 4, 6, ..., 2 20 ]
si5328 44 rev. 1.0 reset value = 0000 0000 reset value = 0000 0000 register 43. bitd7d6d5d4d3d2d1d0 name reserved n31 [18:16] type rr/w bit name function 7:3 reserved reserved. 2:0 n31 [18:16] n31 [18:16]. sets value for input divider for ckin1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 19 valid divider values=[1, 2, 3, ..., 2 19 ] register 44. bitd7d6d5d4d3d2d1d0 name n31_[15:8] type r/w bit name function 7:0 n31_[15:8] n31_[15:8]. sets value for input divider for ckin1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 19 valid divider values=[1, 2, 3, ..., 2 19 ]
si5328 rev. 1.0 45 reset value = 0000 1001 reset value = 0000 0000 register 45. bitd7d6d5d4d3d2d1d0 name n31_[7:0] type r/w bit name function 7:0 n31_[7:0 n31_[7:0]. sets value for input divider for ckin1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 19 valid divider values=[1, 2, 3, ..., 2 19 ] register 46. bitd7d6d5d4d3d2d1d0 name reserved n32_[18:16] type rr/w bit name function 7:3 reserved reserved. 2:0 n32_[18:16] n32_[18:16]. sets value for input divider for ckin2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 19 valid divider values=[1, 2, 3, ..., 2 19 ]
si5328 46 rev. 1.0 reset value = 0000 0000 reset value = 0000 1001 register 47. bitd7d6d5d4d3d2d1d0 name n32_[15:8] type r/w bit name function 7:0 n32_[15:8] n32_[15:8]. sets value for input divider for ckin2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 19 valid divider values=[1, 2, 3, ..., 2 19 ] register 48. bitd7d6d5d4d3d2d1d0 name n32_[7:0] type r/w bit name function 7:0 n32_[7:0] n32_[7:0]. sets value for input divider for ckin1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 19 valid divider values=[1, 2, 3, ..., 2 19 ]
si5328 rev. 1.0 47 reset value = 0000 0000 register 55. bitd7d6d5d4d3d2d1d0 name reserved clkin2rate_[2:0] clkin1rate[2:0] type rr/w r/w bit name function 7:6 reserved reserved. 5:3 clkin2rate[2:0] clkin2rate[2:0]. ckinn frequency selection for fos alarm monitoring. 000: 10?27 mhz 001: 25?54 mhz 010: 50?105 mhz 011: 95?215 mhz 100: 190?435 mhz 101: 375?710 mhz 110: reserved 111: reserved 2:0 clkin1rate [2:0] clkin1rate[2:0]. ckinn frequency selection for fos alarm monitoring. 000: 10?27 mhz 001: 25?54 mhz 010: 50?105 mhz 011: 95?215 mhz 100: 190?435 mhz 101: 375?710 mhz 110: reserved 111: reserved
si5328 48 rev. 1.0 reset value = 0010 0000 register 128. bit d7d6d5d4d3d2 d1 d0 name reserved ck2_actv_reg ck1_actv_reg type rrr bit name function 7:2 reserved reserved. 1 ck2_actv_reg ck2_actv_reg. indicates if ckin2 is currently th e active clock for the pll input. 0: ckin2 is not the active input clock. eith er it is not selected or los2_int is 1. 1: ckin2 is the active input clock. 0 ck1_actv_reg ck1_actv_reg. indicates if ckin1 is currently th e active clock for the pll input. 0: ckin1 is not the active input clock. eith er it is not selected or los1_int is 1. 1: ckin1 is the active input clock.
si5328 rev. 1.0 49 reset value = 0000 0110 register 129. bitd7d6d5d4d3 d2 d1 d0 name reserved los2_int los1_int losx_int type r rrr bit name function 7:3 reserved reserved. 2 los2_int los2_int. indicates the los status on ckin2. 0: normal operation. 1: internal loss-of-signal alarm on ckin2 input. 1 los1_int los1_int. indicates the los status on ckin1. 0: normal operation. 1: internal loss-of-signal alarm on ckin1 input. 0 losx_int losx_int. indicates the los status of the exte rnal reference on the xa/xb pins. 0: normal operation. 1: internal loss-of-signal alarm on xa/xb reference clock input.
si5328 50 rev. 1.0 reset value = 0000 0001 register 130. bitd7 d6d5d4d3d2d1d0 name reserved digholdvalid reserv ed fos2_int fos1_int lol_int type r r r rrr bit name function 7 reserved reserved. 6 digholdvalid digital hold valid. indicates if the digital hold circuit has enou gh samples of a valid clock to meet digital hold specifications. 0: indicates digital hold hist ory registers have no t been filled. the digital hold output frequency may not meet specifications. 1: indicates digital hold history register s have been filled. the digital hold output frequency is valid. 5:3 reserved reserved. 2fos2_int ckin2 frequency offset status. 0: normal operation. 1: internal frequency offset alarm on ckin2 input. 1fos1_int ckin1 frequency offset status. 0: normal operation. 1: internal frequency offset alarm on ckin1 input. 0lol_int pll loss of lock status. 0: pll locked. 1: pll unlocked.
si5328 rev. 1.0 51 reset value = 0001 1111 register 131. bitd7d6d5d4d3 d2 d1 d0 name reserved los2_flg los1_flg losx_flg type r r/w r/w r/w bit name function 7:3 reserved reserved. 2los2_flg ckin2 loss-of-signal flag. 0: normal operation. 1: held version of los2_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by lo s2_msk bit. flag cleared by writing 0 to this bit. 1los1_flg ckin1 loss-of-signal flag. 0: normal operation 1: held version of los1_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by lo s1_msk bit. flag cleared by writing 0 to this bit. 0 losx_flg external reference (signal on pins xa/xb) loss-of-signal flag. 0: normal operation 1: held version of losx_int. ge nerates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by losx_msk bit. flag cleared by writing 0 to this bit.
si5328 52 rev. 1.0 reset value = 0000 0010 register 132. bitd7d6d5d4d3d2d1d0 name reserved fos2_flg fos1_flg lol_flg reserved type rr / w r / w r / w r bit name function 7:4 reserved reserved. 3fos2_flg clkin_2 frequency offset flag. 0: normal operation. 1: held version of fos2_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by fo s2_msk bit. flag cleared by writing 0 to this bit. 2fos1_flg clkin_1 frequency offset flag. 0: normal operation 1: held version of fos1_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by fo s1_msk bit. flag cleared by writing 0 to this bit. 1lol_flg pll loss of lock flag. 0: pll locked 1: held version of lol_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by lo l_msk bit. flag cleared by writing 0 to this bit. 0 reserved reserved.
si5328 rev. 1.0 53 reset value = 0000 0001 reset value = 1100 0010 register 134. bitd7d6d5d4d3d2d1d0 name partnum_ro [11:4] type r bit name function 7:0 partnum_ro [11:0] device id (1 of 2). 0000 0001 1100: si5328 register 135. bitd7d6d5d4d3d2d1d0 name partnum_ro [3:0] revid_ro [3:0] type rr bit name function 7:4 partnum_ro [11:0] device id (2 of 2). 0000 0001 1100: si5328 3:0 revid_ro [3:0] device revision. 0010: revision c others: reserved
si5328 54 rev. 1.0 reset value = 0000 0000 reset value = 0000 0000 register 136. bitd7d6d5d4d3d2d1d0 name rst_reg ical reserved type r/w r/w r bit name function 7 rst_reg internal reset (same as pin reset). note: the i 2 c (or spi) port may not be accessed until 10 ms after rst_reg is asserted. 0: normal operation. 1: reset of all internal logic. outputs disabled or tristated during reset. 6ical start an internal calibration sequence. for proper operation, the device must go through an internal calibration sequence. ical is a self-clearing bit. writing a ?1? to this lo cation initiates an ical. the calibration is com- plete once the lol alarm goes low. 0: normal operation. 1: writing a "1" initiates intern al self-calibration. upon comple tion of internal self-calibra- tion, lol will go low. notes: 1. a valid stable clock (within 100 ppm) must be present to begin ical. 2. if the input changes by more than 500 ppm, the part may do an autonomous ical. 3. see table 10, ?register locations requiring ical,? on page 62 for register changes that require an ical. 5:0 reserved reserved. register 137. bitd7d6d5d4d3d2d1d0 name fastlock type rrrrrrrr/w bit name function 7:1 reserved do not modify. 0 fastlock this bit must be set to 1 to enable fastlock. this improves initial lock time by dynamically changing the loop bandwidth.
si5328 rev. 1.0 55 reset value = 0000 1111 register 138. bitd7d6d5d4d3d2 d1 d0 name reserved los2_en[1:1] los1_en [1:1] type rr/wr/w bit name function 7:2 reserved reserved. 1 los2_en [1:0] enable ckin2 los monitoring on the specified input (2 of 2). note: los2_en is split between two registers. 00: disable los monitoring 01: reserved 10: enable losa monitoring 11: enable los monitoring losa is a slower and less sensitive vers ion of los. see the si53xx family refer- ence manual for details. 0 los1_en [1:0] enable ckin1 los monitoring on the specified input (1 of 2). note: los1_en is split between two registers. 00: disable los monitoring 01: reserved 10: enable losa monitoring 11: enable los monitoring losa is a slower and less sensitive versio n of los. see the si53xx family refer- ence manual for details.
si5328 56 rev. 1.0 reset value = 1111 1111 register 139. bit d7 d6 d5 d4 d3 d2 d1 d0 name reserved los2_en [0:0] los1_en [0:0] reserved fos2_en fos1_en type rr / wr / w r r / wr / w bit name function 7:6 reserved reserved. 5 los2_en [1:0] enable ckin2 los monitoring on the specified input (2 of 2). note: los2_en is split between two registers. 00: disable los monitoring 01: reserved 10: enable losa monitoring 11: enable los monitoring losa is a slower and less sensitive versio n of los. see the si53xx family refer- ence manual for details 4 los1_en [1:0] enable ckin1 los monitoring on the specified input (1 of 2). note: los1_en is split between two registers. 00: disable los monitoring 01: reserved 10: enable losa monitoring 11: enable los monitoring losa is a slower and less sensitive versio n of los. see the si53xx family refer- ence manual for details. 3:2 reserved reserved. 1fos2_en enables fos on a per channel basis. 0: disable fos monitoring 1: enable fos monitoring 0fos1_en enables fos on a per channel basis. 0: disable fos monitoring 1: enable fos monitoring
si5328 rev. 1.0 57 reset value = 0000 0000 reset value = 0000 0000 register 142. bitd7d6d5d4d3d2d1d0 name independentskew1 [7:0] type r/w bit name function 7:0 independ-entskew1 [7:0] independentskew1. eight-bit field that represents a 2?s complement of the phase offset in terms of clocks from the high speed output divider. register 143. bitd7d6d5d4d3d2d1d0 name independentskew2 [7:0] type r/w bit name function 7:0 independ-entskew2 [7:0] independentskew2. eight-bit field that represents a 2?s complement of the phase offset in terms of clocks from the high speed output divider.
si5328 58 rev. 1.0 7. pin descriptions: si5328 pin # pin name i/o signal level description 1 rst ilvcmos external reset. active low input that performs ex ternal hardware reset of device. resets all internal logic to a known state and forces the device reg- isters to their default value. clock outputs are trista ted during reset. the part must be programmed after a reset or power on to get a clock output. see the si53xx family reference manual for details. this pin has a weak pull-up. 2, 9, 14, 19, 20, 30, 33 nc ? ? no connection. leave floating. make no external connections to this pin for normal operation. 3 int_c1b o lvcmos interrupt/ckin1 invalid indicator. this pin functions as a device inte rrupt output or an alarm output for ckin1. if used as an interrupt output, int_pin must be set to 1. the pin functions as a maskable interrupt output with active polarity con- trolled by the int_pol register bit. if used as an alarm output, the pin functions as a los (and option- ally fos) alarm indicator for ckin1. set ck1_bad_pin = 1 and int_pin =0. 0 = ckin1 present 1 = los (fos) on ckin1 the active polarity is controlled by ck_bad_pol . if no function is selected, the pin tristates. note: internal register names are indi cated by underlined italics, e.g., int_pin . see section ?5.register map?. 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 nc nc rst c2b int_c1b gnd vdd xa vdd rate0 ckin2+ ckin2? nc rate1 ckin1+ ckin1? cs_ca scl sda_sdo a1 a2_ss sdi ckout1? nc gnd vdd nc ckout2? ckout2+ cmode gnd pad a0 nc 9 18 19 28 xb lol nc ckout1+
si5328 rev. 1.0 59 4c2bolvcmos ckin2 invalid indicator. this pin functions as a los (and optionally fos) alarm indicator for ckin2 if ck2_bad_pin =1. 0 = ckin2 present 1 = los (fos) on ckin2 the active polarity can be changed by ck_bad_pol . if ck2_bad_pin = 0, the pin tristates. 5, 10, 32 v dd v dd supply supply. the device operates from a 2.5 or 3.3 v supply. bypass capacitors should be associated with the following v dd pins: 50.1f 10 0.1 f 32 0.1 f a 1.0 f should also be placed as clos e to the device as is practical. 7 6 xb xa ianalog reference clock. a tcxo or ocxo should be connected to these pins. refer to the si53xx family reference manual fo r interfacing to the external ref- erence. external reference must be from a high-quality clock source (tcxo, ocxo). frequency of crystal or external clock is set by rate[1:0] pins. 8, 31 gnd gnd supply ground. must be connected to system ground. minimize the ground path impedance for optimal performance of this device. grounding these pins does not eliminate the requirement to ground the gnd pad on the bottom of the package. 11 15 rate0 rate1 i 3-level reference clock rate. three level inputs that select the type and rate of external crystal or reference clock to be applied to the xa/xb port. refer to the si53xx family reference manual for settings . these pins have both a weak pull-up and a weak pull-down; they default to m. l setting corresponds to ground. m setting corresponds to v dd /2. h setting corresponds to v dd . some designs may require an external resistor voltage divider when driven by an active device that will tristate. 16 17 ckin1+ ckin1? imulti clock input 1. differential input clock. this input can also be driven with a single- ended signal. 12 13 ckin2+ ckin2? imulti clock input 2. differential input clock. this input can also be driven with a single- ended signal. pin # pin name i/o signal level description note: internal register names are indi cated by underlined italics, e.g., int_pin . see section ?5.register map?.
si5328 60 rev. 1.0 18 lol o lvcmos pll loss of lock indicator. this pin functions as the active high pll loss of lock indicator if the lol_pin register bit is set to 1. 0 = pll locked 1 = pll unlocked if lol_pin = 0, this pin will tristate. active polarity is controlled by the lol_pol bit. the pll lock status will always be reflected in the lol_int read only register bit. 21 cs_ca i/o lvcmos input clock select/active clock indicator. input : in manual clock selection mode, this pin functions as the manual input clock selector if the cksel_pin is set to 1. 0 = select ckin1 1 = select ckin2 if cksel_pin = 0, the cksel_reg register bit controls this func- tion and this input tristates. if conf igured for input, must be tied high or low. output : in automatic clock selection mode, this pin indicates which of the two input clocks is currently the active clock. if alarms exist on both clocks, ck_actv will indicate the last active clock that was used before entering the digital hold state. the ck_actv_pin reg- ister bit must be set to 1 to reflect the active clock status to the ck_actv output pin. 0 = ckin1 active input clock 1 = ckin2 active input clock if ck_actv_pin = 0, this pin will tristate. the ck_actv status will always be reflected in the ck_actv_reg read only register bit. 22 scl i lvcmos serial clock. this pin functions as the serial clock input for both spi and i 2 c modes. this pin has a weak pull-down. 23 sda_sdo i/o lvcmos serial data. in i 2 c control mode (cmode = 0), this pin functions as the bidirec- tional serial data port. in spi control mode (cmode = 1), th is pin functions as the serial data output. 25 24 a1 a0 ilvcmos serial port address. in i 2 c control mode (cmode = 0), thes e pins function as hardware controlled address bits. the i 2 c address is 1101 [a2] [a1] [a0]. in spi control mode (cmode = 1), these pins are ignored. these pins have a weak pull-down. pin # pin name i/o signal level description note: internal register names are indi cated by underlined italics, e.g., int_pin . see section ?5.register map?.
si5328 rev. 1.0 61 26 a2_ss ilvcmos serial port address/slave select. in i 2 c control mode (cmode = 0), this pin functions as a hardware controlled address bit [a2]. in spi control mode (cmode = 1), this pin functions as the slave select input. this pin has a weak pull-down. 27 sdi i lvcmos serial data in. in i 2 c control mode (cmode = 0), this pin is ignored. in spi control mode (cmode = 1), th is pin functions as the serial data input. this pin has a weak pull-down. 29 28 ckout1? ckout1+ omulti output clock 1. differential output clock with a frequency range of 8 khz to 808 mhz. output signal format is selected by sfout1_reg regis- ter bits. output is differential for lvpecl, lvds, and cml compati- ble modes. for cmos format, both output pins drive identical single-ended clock outputs. 34 35 ckout2? ckout2+ omulti output clock 2. differential output clock with a frequency range of 8 khz to 808 mhz. output signal format is selected by sfout2_reg regis- ter bits. output is differential for lvpecl, lvds, and cml compati- ble modes. for cmos format, both output pins drive identical single-ended clock outputs. 36 cmode i lvcmos control mode. selects i 2 c or spi control mode. 0=i 2 c control mode 1 = spi control mode this pin must not be nc. tie either high or low. see the si53xx family reference manual for details on i 2 c or spi operation. gnd pad gnd gnd supply ground pad. the ground pad must provide a low thermal and electrical impedance to a ground plane. pin # pin name i/o signal level description note: internal register names are indi cated by underlined italics, e.g., int_pin . see section ?5.register map?.
si5328 62 rev. 1.0 table 10 lists all of the register locations that should be followed by an ical after their contents are changed. table 10. register locations requiring ical addr register 0 bypass_reg 0 ckout_always_on 1 ck_prior2 1 ck_prior1 2 bwsel_reg 4h i s t _ d e l 5i c m o s 7 fosrefsel 9h i s t _ a v g 10 dsbl2_reg 10 dsbl1_reg 11 pd_ck2 11 pd_ck1 19 fos_en 19 fos_thr 19 valtime 19 lockt 25 n1_hs 31 nc1_ls 34 nc2_ls 40 n2_hs 40 n2_ls 43 n31 46 n32 55 clkin2rate 55 clkin1rate table 11. si5328 pull up/pull down pin # si5328 pull up/pull down 1rst u 11 rate0 u, d 15 rate1 u, d 21 cs_ca u, d 22 scl d 24 a0 d 25 a1 d 26 a2_ss d 27 sdi d 36 cmode u, d
si5328 rev. 1.0 63 8. ordering guide ordering part number output clock frequency range package rohs6, pb-free temperature range SI5328B-C-GM 8 khz?808 mhz 36-lead 6 x 6 mm qfn yes ?40 to 85 c si5328c-c-gm 8 khz?346 mhz 36-lead 6 x 6 mm qfn yes ?40 to 85 c si5328-evb 8 khz?808 mhz evaluation board ? ?40 to 85 c note: add an r at the end of the device to denote tape and reel options.
si5328 64 rev. 1.0 9. package outline: 36-pin qfn figure 7 illustrates the package details for the si5328. table 12 lists the values for the dimensions shown in the illustration. figure 7. 36-pin quad flat no-lead (qfn) table 12. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.80 0.85 0.90 l 0.50 0.60 0.70 a1 0.00 0.02 0.05 ? ??12o b 0.18 0.25 0.30 aaa ? ? 0.10 d 6.00 bsc bbb ? ? 0.10 d2 3.95 4.10 4.25 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 6.00 bsc eee ? ? 0.05 e2 3.95 4.10 4.25 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jede c outline mo-220, variation vjjd. 4. recommended card reflow profile is per the jede c/ipc j-std-020c specif ication for small body components.
si5328 rev. 1.0 65 10. recommended pcb layout figure 8. pcb land pattern diagram figure 9. ground pad recommended layout
si5328 66 rev. 1.0 table 13. pcb land pattern dimensions dimension min max e 0.50 bsc. e5 . 4 2 r e f . d5 . 4 2 r e f . e2 4.00 4.20 d2 4.00 4.20 ge 4.53 ? gd 4.53 ? x ? 0.28 y0 . 8 9 r e f . ze ? 6.31 zd ? 6.31 notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum ma terial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut, and electro-polis hed stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 9. a 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. card assembly 10. a no-clean, type-3 solder paste is recommended. 11. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si5328 rev. 1.0 67 11. si5328 device top mark mark method: laser font size: 0.80 mm right-justified line 1 marking: si5328q customer part number q = speed code: c see ?8.ordering guide? for options line 2 marking: c-gm c = product revision g = temperature range ?40 to 85 c (rohs6) m = qfn package line 3 marking: yywwrf yy = year ww = work week r = die revision f = internal code assigned by the assembly house. corresponds to the year and work week of the mold date. line 4 marking: pin 1 identifier circle = 0.75 mm diameter lower-left justified xxxx internal code ?
si5328 68 rev. 1.0 d ocument c hange l ist revision 0.9 to revision 1.0 ? removed vdd of 1.8 v. ? updated lock and settling time specs. ? added b speed grade with 808 mhz output frequency.
si5328 rev. 1.0 69 n otes :
si5328 70 rev. 1.0 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive patent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibili ty for errors and omissions, and disclaim s responsibility for any consequences resu lting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warran- ty, representation or guarantee regarding t he suitability of its products for any par ticular purpose, nor does silicon laborato ries assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, in cluding without limitation consequential or incidental damages . silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmle ss against all claims and damages.

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